1. Field of the Invention
This invention relates to apparatus which converts an analog signal to a serial digital signal and converts a serial digital signal to an analog signal, and more particularly, to apparatus for a delta modulation coder and decoder.
2. Description of the Prior Art
A delta modulation coder converts an analog signal, applied to a terminal located at the near end of a communication channel, to a serial digital form particularly suitable for transmission over the communication channel. A delta modulation decoder, located within a similar terminal at the far end, reconstructs the analog signal from the serial digital signal transmitted over the channel.
In a delta modulation coder, the amplitude of an analog input signal is compared to a feedback or reconstructed analog signal, which approximates the analog input signal from a prior time interval. The resulting error, or difference, signal is integrated and sampled to produce a digital output signal. This output signal is binary, i.e. it is either "high" or "low." If at the sampling time, this digital output signal is high, then it indicates that the analog input signal is greater than the feedback signal. On the other hand, if the digital output signal is low, then the analog input signal at the sampling time is less than the feedback signal.
The digital output signal is applied to an output terminal, and is also fed back to a digital integrator. The output of the latter is the feedback signal, which more particularly, is a reconstructed analog signal whose amplitude increases or decreases by a known incremental or discrete amount, referred to as the "step size," in response to each binary state of the digital output signal.
From the output terminal, the digital output signal is transmitted over a communication channel to a decoder, situated at the far end. Within the delta modulation decoder, a digital integrator--substantially identical to that in the coder--integrates the digital output signal incoming from the channel. The result is then applied to a low-pass filter which in response thereto produces a reconstructed analog signal which is substantially equivalent to the analog signal applied to the coder.
At any instant, the digital output of the delta modulation coder defines a corresponding change in the analog input signal and occurs at substantially the same time as that change. However, the feedback signal in the coder and the reconstructed analog signal in the decoder is unable to follow rapid changes in the slope of the analog input signal. Consequently, as the slope of the analog input signal increases, the magnitude of both the feedback signal in the coder and the reconstructed analog signal in the decoder disadvantageously and increasingly lags behind (in time) that of the analog input signal. This condition is known as "slope overload." It basically arises because (1) the coder's digital output signal is binary and (2) the coder is operated at a fixed maximum speed dictated by the frequency of the sampling clock. Consequently, changes in the feedback signal in the coder and the reconstructed analog signal in the decoder are restricted by the binary input to one discrete step-size at a time and to a fixed maximum rate governed by the clock frequency. Thus, during an interval of slope overload, both the feedback signal and the analog signal reconstructed at the receiving end become significantly distorted.
Various solutions aimed at eliminating slope overload have been put forth in the art. One such solution is to incorporate a slope limiter in the input circuit of the delta modulator to limit the slope of the analog input signal to a value below which slope overload will not occur. See U.S. Pat. No. 4,008,435 (issued Feb. 15, 1977 to T. Oshima et al). While this technique does prevent slope overload from occurring, the slope limiter significantly slows the response of the delta modulator to a rapidly changing analog input signal.
Another solution is to increase the frequency of sampling the integrated error signal to, for example, 8 megahertz or greater for the transmission of voiceband signals. However, as the sampling rate is increased, so is the bandwidth required to transmit the digital output signal. Moreover, analog integrators exhibit increased instability at increased sampling frequencies. To attain stability at an increased sampling frequency, increased circuit sophistication becomes necessary and substantial added costs are incurred.
A further solution is to increase the step sizes (as the input signal magnitude increases) in a logarithmic basis. This is known as "companding." See, for example, J. C. Candy, W. H. Ninke and B. A. Wooley, "A Per-Channel A/D Converter Having 15-Segment .mu.-255 Companding," IEEE Transactions on Communications, VOL. COM-24, No. 1, January 1976, pp. 33-42; and U.S. Pat. No. 3,925,731 (issued Dec. 9, 1975 to R. C. Brainard et al and hereinafter referred to as the '731 patent). Unfortunately, since the step sizes are small when the feedback signal amplitude is small, companding has little effect whenever there is rapid changes of a low amplitude input signal. One solution which overcomes this, and thereby reduces slope overload, involves increasing the step size whenever slope overload is detected. See R. H. Bosworth and J. C. Candy, "A Companded One-Bit Coder for Television Transmission," The Bell System Technical Journal, Vol. 48, No. 5, May-June, 1969, pp. 1459-1479, and J. E. Abate "Linear and Adaptive Delta Modulation," Proceedings of the IEEE, Vol. 55, No. 3, March 1967, pp. 298-308. A companded coder which employs this technique is described in U.S. Pat. No. 4,042,921 (issued to P. L. Smith on Aug. 16, 1977). There, the step size is logarithmically adjusted based on the average peak slope of the analog input signal rather than the instantaneous slope. Unfortunately, coders which rely on varying step sizes tend to be violently unstable during slope overload.